IBM said on June 25 it has developed the world’s first sub-nanometer chip process, a technology built on transistors stacked vertically in three dimensions that leapfrogs the industry to a 0.7-nanometer node. The announcement, reported by Reuters, pushes the limits of semiconductor physics another step forward—though commercial production, if it ever comes, remains years away.
The technology packs nearly 100 billion transistors onto a chip the size of a fingernail, roughly double the density of the two-nanometer chip IBM announced in 2021. In early testing, the company said, the design delivers up to 50% better performance or cuts energy consumption by as much as 70%, and it shrinks the area of SRAM memory cells by 40%.
The approach abandons the planar layout that has defined chip design for decades. Instead of placing transistors side by side on a flat surface, IBM stacks them vertically, so devices sit on top of one another and density grows upward rather than outward. Chipmakers have been moving toward this architecture, known in the industry as complementary FETs, or CFETs, as they exhaust the benefits of shrinking features on a flat plane. Intel, Taiwan Semiconductor Manufacturing Co. and Samsung have all signaled plans for stacked transistors in future nodes, but IBM claims to have demonstrated the approach first at sub-nanometer dimensions.
IBM has been a research leader in semiconductors long after it stopped being a manufacturer. The company sold its chip-making business to GlobalFoundries in 2014 and now licenses its technology instead of building it. Its research center in Albany, New York, has produced a string of advances, including the 2021 two-nanometer breakthrough, which used gate-all-around transistors to fit 50 billion transistors on a fingernail-sized chip.
The significance is as much about physics as about business. Transistors have been shrinking for six decades, and the industry has repeatedly declared the end of Moore’s law only to find another trick. Vertical stacking is one of the few remaining tricks: it adds density without requiring ever-smaller feature sizes, which are approaching the limits of what light-based lithography can draw.
IBM’s announcement is not a product. The company does not operate fabs at scale, and the technology will not appear in consumer devices anytime soon. IBM executives said commercial production is at least five to ten years away, a timeline that puts the process beyond the current planning horizons of most chipmakers.
The research does have commercial pathways. IBM’s two-nanometer design was licensed to Rapidus, a Japanese startup backed by government money that aims to build advanced chips in Japan. Analysts said a similar arrangement could follow for the new technology, giving IBM a way to monetize research without the enormous cost of building a fab.
The timing is notable. The foundry industry is locked in an expensive race: TSMC is building factories in the U.S., Japan and Germany, Samsung is spending heavily to catch up, and Intel is trying to reclaim manufacturing leadership under government subsidies. IBM sits outside that race, funding its research at a scale the foundries can only envy for its focus.
The 0.7-nanometer figure deserves context. Node names have drifted from physical measurements over the years; a “two-nanometer” chip today does not have features that are literally two nanometers wide. The sub-nanometer label is IBM’s claim to have crossed a threshold the industry has discussed for years, and rivals may dispute both the naming and the metrics.
What cannot be disputed is the direction. AI workloads are voracious consumers of compute, and the chips that serve them are running into power and heat limits. A process that cuts energy use by 70% would change the economics of data centers, which are increasingly constrained by electricity rather than by silicon.
IBM’s announcement lands in a year when the industry is debating how much further shrinking can go. Some researchers argue that new materials and architectures—including photonics and neuromorphic designs—will matter more than node size. IBM’s bet is that a few more generations of conventional scaling remain, and that vertical transistors are the way to get there.
The work at Albany is part of a broader American effort to rebuild semiconductor research. The CHIPS and Science Act directed billions of dollars into chip research and development, and the Albany facility was chosen as a flagship site for the National Semiconductor Technology Center’s program on extreme ultraviolet lithography. IBM’s researchers work alongside those efforts, and the new process draws on equipment, funding and expertise assembled for the national push.
For now, the 100 billion transistors on a fingernail are a laboratory result, a proof point rather than a product. But the same was true of IBM’s two-nanometer announcement in 2021, and that technology found its way into a national project in Japan. The industry has learned not to dismiss IBM’s research, even when the products take a decade to arrive.
