The note from Morgan Stanley landed on clients’ screens with a forecast that a year ago would have been dismissed as wishful thinking: AMD’s next server processor will ship more units in 2027 than Nvidia’s flagship server CPU. The bank expects production of AMD’s EPYC Venice chip to reach 6.75 million units in 2027, roughly 17% more than the 5.75 million units it projects for Nvidia’s Vera processor.
The gap is narrow but symbolic. For most of the past decade, AMD and Nvidia have been rivals in adjacent lanes — AMD selling server CPUs to the same data centers that buy Nvidia’s GPUs — and Nvidia’s data-center franchise has grown so large that its CPU business is often treated as an afterthought. Vera, the next-generation CPU Nvidia designed to sit beside its Rubin line of accelerators, is the company’s answer to the question of whether it can extend its platform dominance into the processor that orchestrates every AI workload. The Morgan Stanley numbers, if right, would mean AMD wins the server-socket race in the AI era even while Nvidia continues to dominate the accelerator silicon inside the same boxes.
The bank’s case rests on two pillars. The first is AMD’s expanding share of server sockets as cloud operators seek a second source of CPU supply and push back against single-vendor dependence. AMD’s share of the server CPU market has climbed steadily over several years to roughly a quarter of the market, and hyperscale buyers have shown a willingness to shift workloads between suppliers when price and power efficiency move. The second is the peculiar economics of AI servers, where a CPU still orchestrates the GPUs around it; every accelerator Nvidia sells needs a host processor beside it, and AMD has made the case that its EPYC line can play that role more cheaply than Nvidia’s own silicon.
The note also carries a forecast for the packaging bottleneck that has constrained AI chip supply for three years. Morgan Stanley projects TSMC’s CoWoS advanced packaging capacity will rise to about 200,000 wafers per month in 2027, with Nvidia remaining the foundry’s largest customer for that capacity. CoWoS is the technology that stacks high-bandwidth memory alongside logic chips, and its limited supply has forced chip designers to queue for capacity and pay premiums to secure it. A climb to 200,000 wafers a month would be a substantial expansion from current levels and would ease the allocation squeeze that has shaped product roadmaps across the industry.
The backdrop is a server CPU market that has been in quiet upheaval. Intel, the longtime incumbent, still sells more server processors than anyone, but its share has eroded for years as AMD’s EPYC line won design wins on core counts, memory bandwidth, and power efficiency. Into that fight has come Nvidia, which sells its CPUs as the natural companion to its own accelerators and has pushed into networking and systems to sell complete racks. The Morgan Stanley forecast essentially projects a two-horse race between AMD and Nvidia at the top of the server market, with Intel’s own next-generation parts fighting for the remainder — a shape that would have been hard to imagine when Intel’s Xeon line was the industry default.
Analysts cautioned that production forecasts at this distance should be read with care. Chip volumes in a given year depend on customer orders, macro demand, and the pace of platform transitions, and a single note can move in either direction as the year approaches. But the direction of the Morgan Stanley estimate matters. AMD’s Venice chip, built on the company’s newest Zen architecture, is designed to be the workhorse of the next server generation, and the bank’s expectation that it outshipping Vera reflects a view that cloud operators will standardize on AMD sockets while mixing accelerator suppliers underneath.
For AMD, Venice is the vanguard of a push to sell complete AI server platforms — CPU plus its MI-series accelerators — to data centers that increasingly want one vendor’s parts working in lockstep. For Nvidia, Vera is the counter: a CPU designed to defend the platform lock-in that has made its data-center business the most profitable in semiconductors. The two companies are also fighting over software ecosystems, memory standards, and the engineers who write the frameworks that make AI servers run.
Semiconductor analysts said the packaging numbers are the more consequential part of the note, because CoWoS capacity determines how many AI accelerators can physically be built, regardless of who designs them. If TSMC reaches 200,000 wafers a month by 2027, the industry will produce meaningfully more accelerators than it does today, which cuts two ways: more supply for Nvidia’s customers, and more room for AMD and custom-chip designers to grow without stealing sockets from each other.
The race now moves to deliveries. AMD has said little publicly about Venice’s customer commitments, and Nvidia has not commented on the Morgan Stanley projections. What is clear is that the fight over the AI server has moved from the accelerator alone to the whole machine — the CPU, the memory, the packaging, and the software that binds them. The bank’s forecast is one firm’s view of how that fight ends in 2027; the other firms will have their own numbers, and the market will have the final word.
