The base die is the least discussed layer of a high-bandwidth memory stack and, as of this week, the most contested. It is the logic chip at the bottom of the tower, the one that carries the wiring to the accelerator and, in the newest designs, the controller that decides how data moves.
Samsung Electronics has agreed to do something it has never done: let a competitor make it. According to Seoul Economic Daily on October 18, Samsung will produce the base die for Nvidia’s next custom high-bandwidth memory on TSMC’s 3-nanometer process. It is the first time the company has brought TSMC into any stage of its memory manufacturing.
The instruction applies to the whole supplier base. Nvidia has asked Samsung, SK hynix and Micron to use TSMC’s 3-nanometer process for base dies and sixth-generation DRAM for the core dies stacked above them, according to the report. Same process, same electrical behavior, three suppliers.
The reason is qualification. Nvidia validates memory against a set of timing, power and thermal parameters, and each new supplier costs months of testing. A common base die process gives the company one set of numbers to design against, stacks that can be swapped without requalifying the module, and considerably more room to play suppliers against each other on price.
The architecture made the request possible. NVHBM, which Nvidia introduced in August, moves the memory controller off the graphics processor and onto the base die. In every earlier generation that controller sat on the accelerator itself, taking up area and power on the most expensive silicon in the system.
That area is not cheap. An accelerator die is bounded by the size of a lithography field, so every square millimeter given to memory management is a square millimeter unavailable for arithmetic. Shifting the controller into the base die converts a cost on the GPU into a component of the memory package, and it changes what the base die has to be.
It has to be a logic chip. A controller running at the data rates the newest standard targets cannot be built on the mature nodes that memory makers have used for base dies. It needs a leading-edge process for density and power, which is why a foundry enters a part of the supply chain it has never supplied.
For Samsung the decision is a concession with a schedule attached. Its own foundry has struggled with yields at advanced nodes, and a customer program that slips is worse than an outsourced one that ships. Buying the process from TSMC keeps the NVHBM allocation on time and keeps Samsung inside a program it might otherwise have lost.
The economics move with the design. Value migrates from the DRAM core, which is increasingly a commodity manufactured by three companies to a common specification, toward the logic that controls it. The memory maker keeps the stack, the assembly and the test. The foundry takes a share of what used to be a fully integrated part.
TSMC gains content in a place it already earns. The company packages these stacks through its chip-on-wafer-on-substrate lines, and a base die built on its 3-nanometer process adds silicon revenue to the same customer relationship. The base die is small compared with the accelerator, but there is one for every stack, and high-bandwidth memory ships by the million.
Nvidia’s interest extends past engineering. If three suppliers build the same base die on the same process, differences between their products narrow to the DRAM core and the assembly yield. That compresses the price spread the memory makers have used to protect margins, and it reduces the cost of switching when one of them has a bad quarter.
What stays inside Samsung is telling. Its standard high-bandwidth memory, the parts sold to everyone else, continues on its own lines and its own base dies. The arrangement with TSMC covers Nvidia’s custom part specifically, which makes it a customer-driven exception rather than a change of strategy.
The risks are ordinary ones. Advanced-node capacity at TSMC is allocated years ahead, and a base die order competes with every other customer for the same wafers. Base dies are large, which makes yield a cost issue, and a 3-nanometer base die costs more than the mature-node part it replaces.
There is also the question the report leaves open. SK hynix and Micron were asked to follow the same route; Samsung has accepted. Whether the other two agree determines whether Nvidia gets the uniformity it wants or a hybrid supply base with two processes and two sets of qualifiers.
For the memory industry the arrangement shifts a boundary that has held for a decade. The base die was an afterthought, a piece of wiring built wherever it was convenient. It now carries the control plane of the memory system, and the control plane belongs to a foundry on a process the memory makers do not own.
