Cadence Design Systems introduced a family of artificial-intelligence models for chip design on Monday, and the most consequential specification is not a benchmark score. The models run on the customer’s own hardware. Design data does not leave the building.
The product is called Maestro, a suite tuned in collaboration with Nvidia and aimed at the stages where chip design consumes the most engineering time: writing and debugging register-transfer-level code, building verification testbenches, fixing timing violations and closing physical design. Cadence says quality on certain design tasks improves by roughly 30% against its previous tools, a figure the company has not published supporting data for and that customers will test on their own blocks.
The architecture decision is the story. Every large model shipped by a software vendor over the past two years has run in that vendor’s cloud, because that is where the vendor controls the weights, the updates and the billing meter. Chipmakers have resisted. A netlist is a description of a product two years from production; a floorplan reveals how a company intends to compete. Sending either to a third party requires legal review that can take a year, and some foundry agreements forbid it outright.
So Cadence built the deployment model around a constraint its customers would not negotiate. Maestro runs on GPU clusters the customer owns or leases, inside its own network, and Cadence licenses the models rather than the compute. That inverts the usual cloud economics: the vendor gives up the markup on inference and keeps the licence, and the customer pays for hardware separately.
Nvidia’s interest in the arrangement is direct. Local deployment means the customer buys GPUs, and Cadence’s tuning work makes those GPUs useful for a workload that previously ran on CPUs. Nvidia’s own design teams have been among the earliest users of machine learning in physical design, and the company has spent years arguing that accelerated computing belongs in every engineering workflow, including the ones that build its competitors.
Cadence’s existing AI products show where Maestro fits. Cerebrus automates the iterative search for a better floorplan, Verisium applies models to verification debug, and Optimality handles system-level tradeoffs. Those are point tools with machine learning inside. Maestro is the company’s attempt to put a general model underneath all of them, so that the same engine reads a specification, proposes a design change and checks whether the change breaks something else.
The competitive map is small. Synopsys, the larger of the two American EDA suppliers, has its own AI stack and closed its acquisition of Ansys, which brought simulation into the same portfolio. Siemens EDA sells its own tools. Between them the three companies collect most of what the semiconductor industry spends on design software, a market that grows with the complexity of each new process node rather than with unit volumes.
Analysts said the 30% figure is the kind of claim that EDA customers evaluate slowly. A wrong answer in a code-completion tool wastes a minute. A wrong answer in timing closure can cost a mask set, and a mask set at a leading-edge node costs tens of millions of dollars. Verification is where the tolerance for error is lowest and where the labour savings are largest, which is why every vendor’s first credible deployments have been in debug rather than in synthesis.
There is a second audience for the local-deployment design. Export controls have made the geography of design software a policy question, and Washington has twice restricted sales of advanced EDA tools to Chinese customers before narrowing the scope after industry objections. A product that runs inside a customer’s data centre is easier to audit and easier to switch off than a service, a property regulators tend to like and customers tend to notice.
Cadence reported about $4.6 billion in revenue in 2024 and has grown in the years since on the strength of hardware-assisted verification and IP licensing as much as on software subscriptions. Those businesses are cyclical; design starts rise and fall with capital spending. A model that improves engineering productivity is the sort of product that sells through a downturn, because headcount is the line item chipmakers cut last.
The commercial model also differs from the way design software has been sold for thirty years. EDA licences are subscription contracts, renewed annually and priced by seat and by capability tier, and customers plan for them the way they plan for payroll. A model that improves as it sees more of a customer’s designs invites a different arrangement, one where the vendor charges for outcomes and the customer has to decide how much of its design history to trade for the improvement. Cadence has not described how it will price Maestro, and the answer will determine whether it sells as an upgrade to an existing seat or as a new line item that procurement resists.
The open question is not whether models can help design chips. It is whether a model vendor can keep pace with the process technology it is supposed to accelerate. Each node changes the rules the model learned, and the customers adopting Maestro first are the ones working on the nodes where the training data does not yet exist. That is a hard place to sell a 30% improvement, and the place where the licence will be earned or lost.
