SEOUL — The number on the slide was 41 seconds. On the same plot, in smaller type, was the one it replaced: 18 hours.
Samsung Electronics presented the comparison on Nov. 10 at Nvidia’s AI Day in Seoul, part of a running series of developer events the chip designer has staged in capitals around the world. The work was a thermal simulation of a semiconductor device, the kind of calculation that engineering teams run repeatedly while deciding how a chip should be laid out, and Samsung attributed the speedup to accelerated computing built with Nvidia’s hardware and software.
A thermal simulation asks a simple question with an expensive answer: where does the heat go. Current through a transistor generates it, metal layers conduct it, packaging and the board absorb it, and the pattern that results determines whether a part runs at its rated clock or throttles. Getting the answer requires solving partial differential equations across a mesh with millions of cells, and the solvers that do the work have historically been limited by the clock speed of a handful of server cores.
That constraint shaped how design teams worked. Engineers would queue simulations overnight, or run a coarse version and refine later, or simply skip design points that looked expensive. Reducing an 18-hour job to under a minute changes the economics of the loop: an engineer can test a variant, look at the result and test another one in the time it takes to review a document.
Samsung is not the first company to make this argument. Nvidia has spent several years selling the same proposition to manufacturers in automotive, aerospace and electronics, and its simulation libraries and GPU-accelerated solvers have been adopted by a long list of industrial firms. The pitch is that the GPU is a general-purpose machine for physics as much as a training device, and that the addressable market for that work is larger than the market for language models.
For Samsung the demonstration carries weight beyond the benchmark. The company runs one of the two or three largest chipmaking operations in the world, spanning memory, logic and the foundry business that manufactures designs for outside customers. Its engineers are both a large consumer of simulation software and a supplier of the memory that accelerated systems require, which gives it a reason to appear on stage at an Nvidia event that its foundry rival did not attend.
The same session produced a second data point. Samsung disclosed a chip built on its 2-nanometer process for DEEPX, a Korean AI chip startup, with power consumption of about 5 watts, and said the part had been named to the CES 2027 innovation list. Five watts is a different regime from the kilowatts that data center accelerators draw, and it points at cameras, robots and edge devices where the constraint is a battery or a sealed enclosure.
Samsung’s foundry division has been pushing 2-nanometer production as its answer to Taiwan Semiconductor Manufacturing Co., which holds the largest share of advanced logic manufacturing. Winning designs from AI startups is one way to fill capacity while the largest customers negotiate. Winning them at low power is the specific claim Samsung wants on the record, because edge AI is where its memory business and its logic business can be sold together.
The third item was a status update. Samsung said its Texas fab is close to running pilot production for Tesla’s chips. That project has been watched closely since it was announced, both as a test of Samsung’s ability to execute outside Korea and as a test of whether Tesla can build a vertically integrated supply chain for the silicon in its vehicles and its robotics program.
Those three announcements share a theme that the industry has been circling for two years: the bottleneck in advanced computing has moved from the design of a chip to everything around it. Manufacturing yield, thermal behavior, packaging, power delivery and the software that connects them now determine how fast a product reaches a market. A simulation that runs in 41 seconds instead of 18 hours does not make a better transistor. It shortens the path to one.
Whether that translates into foundry orders is the question Samsung cannot answer from a stage. Its 2-nanometer process has reportedly struggled with yield, and the customers who matter most for volume are the ones least willing to accept a learning curve. A startup designing a low-power inference part has more tolerance for a new process than a hyperscaler with a fixed launch date.
The competitive picture is also moving. TSMC is advancing its own node roadmap and has expanded its Arizona investment, Intel is rebuilding its foundry business around a government-backed manufacturing push, and the gap between the leading edge and the rest has widened rather than narrowed. Samsung’s position depends on convincing customers that its process, its packaging and now its design tooling are close enough to the alternative.
For Nvidia, the Seoul event is part of a broader effort to make its platform the default for engineering work as well as model training. The company’s position in accelerators gives it an installed base that its simulation software can address, and each industrial customer that standardizes on its libraries is a customer that will not switch casually.
The 41-second figure will be repeated at conferences for the next year. What it does not show is how many simulations Samsung actually runs, or whether faster iteration produces better chips or merely more of them. That answer arrives in products, on a schedule measured in quarters, and no slide has ever displayed it.
